The present invention relates generally to integrated circuit device design techniques and, more particularly, to failure detection of integrated circuit layouts through a geometry-based, electrical hotspot detection technique.
In designing an integrated circuit (IC), engineers or designers typically rely on computer design tools to help create an IC schematic or design, which can include a multitude of individual devices, such as transistors, coupled together to perform a certain function. To actually fabricate the IC in or on a semiconductor substrate, the IC schematic must be translated into a physical representation or layout, which itself can then be transferred onto a semiconductor substrate. Computer aided design (CAD) tools can be used to assist layout designers with translating the discrete circuit elements into shapes, which will embody the devices themselves in the completed IC. These shapes make up the individual components of the circuit, such as gate electrodes, diffusion regions, metal interconnects and the like.
The software programs employed by the CAD systems to produce layout representations are typically structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, the design rules are determined by certain processing and design limitations based roughly on the patternability of layout designs. For example, design rules may define the space tolerance between devices or interconnect lines. Once the layout of the circuit has been created, the next step in manufacturing the IC is to transfer the layout onto a semiconductor substrate. Optical lithography or photolithography is a well-known process for transferring geometric shapes onto the surface on a semiconductor wafer. The photolithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor substrate or wafer. A reticle or mask having fully light non-transmissive opaque regions (which are often formed of chrome) and fully light transmissive clear regions (which are often formed of quartz) is then positioned over the photoresist coated wafer.
The mask is placed between a radiation or light source, which can produce light of a pre-selected wavelength (e.g., ultraviolet light) and geometry, and an optical lens system, which may form part of a stepper apparatus. When the light from the light source is directed onto the mask, the light is focused to generate a reduced mask image on the wafer, typically using the optical lens system, which may contain one or several lenses, filters, and/or mirrors. This light passes through the clear regions of the mask to expose the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed or unexposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern, which defines the geometries, features, lines and shapes of that layer. This pattern can then be used for etching underlying regions of the wafer.
As indicated above, technology must provide ground rules to designers on order to ensure that designs passing the defined ground rules are in fact manufacturable. Current processes perform simulations and hardware measurements on limited topologies (e.g., typically varying one parameter) to determine allowed edge relations. However, as the size of design features continues to scale below the wavelength of the patterning light source (a situation that is becoming progressively worse), more of the layout needs to be examined to determine whether the design is manufacturable.